IA32 System Programming - Part I

System Architecture Overview

Except the well-known general purpose registers and segmentation registers, IA32 x86 incorporates a set of system registers, data structures, and instructions in its system level architecture. Only privileged code is allowed to access these system level resources. This architecture includes:

• EFLAGS register controls I/O, maskable interrupts, debugging, task switch and virtual-86 mode.
• Control registers (CR0~CR4) control the operation mode of the processor and performs memory paging.
• Debug registers (DR0~DR7) and instructions provides facilities for system debugging code and performance monitoring.
• Descriptor registers (GDTR, LDTR, IDTR, TR), descriptor tables, and related load/store instructions control segmented memory management.