IA32 System Programming - Part VII

Task Switch

A processor supported task context (or state) is defined as a TSS structure, which includes the following fields:

Dynamic Fields

• Segment selector registers (CS, SS, DS, ES, FS, and GS).
• General purpose registers (EAX, EBX, ECX, EDX, EBX, EBP, ESP, ESI, and EDI).
• The processor status register (EFLAGS).
• The program counter register (EIP).
• Links to previous task.

Static Fiels

• Task LDT (local descriptor table) segment descriptor.
• Task page directory base register (CR3/PDBR)
• Stack pointers for privilege level 0~2.

Static TSS fields are usually initialized by system software during task creation time.

There are 4 cases the processor will transfer execution to another task:

• A far call or jump directly to a TSS descriptor in the GDT.
• A far call or jump indirectly to a task-gate descriptor in the GDT or the current LDT.
• An asserted interrupt or exception vector points to a task-gate descriptor in the IDT.
• An "iret" when the EFLAGS::NT flag is set.

Analogous to the call gate descriptor for indirect access to privileged procedures, the task gate descriptor is defined for protected indirect reference to tasks. CPL, RPL and DPL of target TSS descriptor are checked in a direct TSS call or jump. CPL, RPL and DPL of the task gate descriptor are checked in an indirect task switch. Processor states are saved or restored into/from the task context in the TSS structure.