When the CR0::PE bit is set, the processor will switch to protected mode and enables segmentation. There is no single control bit to disable protected mode once the processor enters protected mode. Similarly, when the CR0:PG bit is set, the processor enables paging and there is no single mode-bit to disable paging mechanism.
In protected mode, the processor always performs its execution within a task context. There is at least one task defined in the system. In addition, except explicit scheduling policy performed by the system software, task dispatching, execution, and suspension are supported by the processor task management facility. A task context is defined as a structure called TSS (task state segment), which contains code execution space information (a code segment, one or more data segment, and a stack segment) and task state information (processor status, general purpose registers, program counter, page directory base, local descriptor base, I/O map base, and a link to previous task). Program control transfer between tasks is supported by the processor through either the direct task switch or the indirect way called task-gate. Task switch mechanism will be depicted in Part VII later.
Program control transfer without explicit user task switch involves inter-segment call, inter-privilege-level call, fast system call, and interrupt/exception. The former two will be depicted in Part IV and Part V. Fast system call will be discussed in Part VI. And interrupt/exception will be left as future topic temporarily. The corresponding formal documentation of these sections could be found in the IA32 Intel Architecture Software Developer’s Manual – Volume 3: System Programming Guide.
可以請教您,在您的blog中的心智圖的圖檔是用什麼軟體繪製的呢???
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