IA32 System Programming - Part II

Segmentation and Paging Overview

IA32 protected mode memory management is divided into two parts: segmentation and paging. Segmentation provides hardware supported linear address space partitioning for isolation and deployment of code, data, and stack sections. Paging provides mechanism for on-demand virtual to physical memory mapping which could be utilized to isolate and protect memory between multiple tasks. Minimal form of segmentation is required in IA32 protected mode. So there is no way to disable segmentation. Paging is, however, an optional function for system software.

Segmentation starts by using a 16-bit segment selector and a 32-bit offset to locate a particular byte in the processor’s linear address space. The “selector:offset” pair is called a logical address (also called the far pointer). A selector is used to identify/lookup a segment descriptor in the descriptor table. The TI field in the selector specifies whether to lookup in a global descriptor table (GDT) or in the local descriptor table (LDT). The GDT and LDT base addresses are specified by the GDTR and LDTR registers respectively. There are other types of descriptor tables, but they are not involved in the logical to linear address translation so are out of the scope here temporarily. The RPL field specifies the requestor’s privilege level and is involved in the complex privilege level checking facility we’ll depicted in the next few parts of this IA32 system programming series. Each entry of the descriptor is fixed to 8-bytes in size. The base and limit fields of a descriptor specify the base and range of the segment in the processor linear space. The flags field of a descriptor specifies the descriptor type. When the S descriptor flag is set, the descriptor type is ether a code or a data segment. When the S descriptor flag is clear, the descriptor is a system descriptor which includes system segment descriptors (LDT segment descriptor, TSS descriptor) and gate descriptors (call-gate descriptor, task-gate descriptor, interrupt-gate descriptor, and trap gate descriptor). Gate descriptors are some kind of “gate” which indirectly points to a code entry point in a code segment or a TSS segment.

If paging is not enabled, the linear address space is directly mapped to the physical address space of the processor. If enabled, the mapping is indirectly through levels of page tables. When paging is enabled, the linear address space is divided into fixed-size pages. The processor’s system register specifies the size of a page configured by the system software, which could be 4K, 2M , or 4M bytes. If the page of a linear address is not currently allocated with a physical page, a page fault exception will be asserted. The corresponding exception handler of system software typically catches the exception then allocates a physical frame and/or copy data from the disk for the linear address. The first level of page table is called a page directory, whose base address is specified by the system software in the CR3 system register. To minimize bus access required for address translation, the most recently translated entries are cached in the translation look aside buffers (TLBs). When the CR3 registers is reloaded, the processor will flush and invalidates previously cached contents so the system software is safe to discard cache coherency problems about TLBs.

The whole story above is abbreviated in the following figure.